1. Field of the Invention
The present invention relates to a semiconductor device, and more particularly, to a method for fabricating a semiconductor device having two or more optimized regions.
2. Discussion of the Related Art
The self-aligned contact technique employed in processes for fabricating a semiconductor device, such as a DRAM, is a technique for forming sidewalls of a gate electrode in a cell region with a nitride which has a better selectivity than an oxide to secure an adequate process for contact etching. In this regard, a conventional method for fabricating a semiconductor device will be explained with reference to the attached drawings.
FIGS. 1a-1c illustrate sectional views showing steps for fabricating a conventional semiconductor device. As shown in FIG. 1a, when forming sidewalls according to the conventional method, a nitride is deposited on an entire surface of a semiconductor substrate 1 having a gate electrode 2 formed thereon. The nitride is then dry etched into nitride sidewalls 3 at sides of the gate electrode 2. Then, as shown in FIG. 1b, an oxide film 4 is deposited on the entire resulting surface. Portions of the oxide film 4 on an impurity region at a predetermined part of the semiconductor substrate 1 is selectively etched to form a contact hole. Then, a metal layer is formed on the entire resulting surface including the contact hole. The metal layer is subjected to patterning to form metal wiring.
In the aforementioned conventional self-aligned contact technique using sidewalls, each of the material for forming the sidewalls at sides of the gate electrode 2 and the material for forming an interlayer insulating film for forming the metal wiring has a large etch selectivity with respect to each other. Therefore, even if there is a slight misalignment in the contact etch process, it does not cause any difficulty in the formation of the contact hole.
However, the use of an identical nitride in the formation of sidewalls for an element in a cell region as well as for an element in a peripheral circuit has caused problems as follows.
First, the use of nitride in the formation of sidewalls for an element in a peripheral circuit increases an overlap capacitance of the gate-source electrodes, and causes an adverse effect on the device due to an increase in hot carrier generation. Second, the decrease in sidewall size for obtaining a larger contact hole in the cell region degrades performance of the element in a peripheral circuit. On the other hand, an increase in the sidewall size with a decrease in the contact hole size causes defects in the wiring.